FusionCell: Cross-Attentive Fusion of Layout Geometry and Netlist Topology for Standard-Cell Performance Prediction

Standard cells form the building blocks of digital circuits, so their delay and power critically influence chip-level performance; yet characterization (can be understood as evaluation of cell delay and power) still relies on slow simulation sweeps, and many fast predictors ignore layout geometry, missing coupling and layout-dependent effects. The challenge is to jointly represent layout geometry and netlist topology so models capture fine-grained spatial details together with structural connectivity for accurate performance prediction. We introduce \textbf{FusionCell}, a dual-modality predictor that treats routed layout geometry and netlist topology as inputs and fuses them explicitly in a unified model. A DeiT encoder processes three-layer routed layouts, while a graph transformer models heterogeneous device/net graphs. The modalities are integrated through a \textbf{topology-guided} mechanism, where the netlist acts as a structural ``map'' to actively query relevant physical regions in the layout for joint geometric and topological reasoning. We build a 7nm dataset based on the ASAP7 PDK with over 19.5k cells spanning 149 types using automatic tools, targeting six metrics: signal rise/fall delay, transition, and power. Experimental results demonstrate that \textbf{FusionCell} reduces regression error (average MAPE 0.92\%) and improves Spearman/Kendall ranking over baselines, while accelerating the characterization process by orders of magnitude compared to circuit simulation.

Modern computer chips are built from many small reusable blocks called standard cells. Before these blocks can be used in a chip, engineers need to know how fast they operate and how much power they consume. Today, obtaining these measurements usually requires detailed circuit simulations, which are accurate but can take a long time when many cell designs must be checked. This paper introduces FusionCell, a machine learning method that predicts the speed and power of standard cells much faster. Instead of looking only at the circuit connections or only at the physical drawing of the cell, FusionCell uses both sources of information together. The circuit connections tell the model which parts of the cell are electrically related, while the physical layout shows how wires and shapes are arranged. By combining these views, the model can better understand how a cell will behave. We test FusionCell on a large dataset of modern 7-nanometer standard-cell designs. The results show that it can predict several important speed and power measurements with about 1% average error, while being much faster than traditional simulation-based characterization. This can help chip designers explore more design options and improve chip performance more efficiently.