AutoSizer: Automatic Sizing of Analog and Mixed-Signal Circuits via Large Language Model (LLM) Agents

The design of Analog and Mixed-Signal (AMS) integrated circuits remains heavily reliant on expert knowledge, with transistor sizing a major bottleneck due to nonlinear behavior, high-dimensional design spaces, and strict performance constraints. Existing Electronic Design Automation (EDA) methods typically frame sizing as static black-box optimization, resulting in inefficient and less robust solutions. Although Large Language Models (LLMs) exhibit strong reasoning abilities, they are not suited for precise numerical optimization in AMS sizing. To address this gap, we propose \textsc{AutoSizer}, a reflective LLM-driven meta-optimization framework that unifies circuit understanding, adaptive search-space construction, and optimization orchestration in a closed loop. It employs a two-loop optimization framework, with an inner loop for circuit sizing and an outer loop that analyzes optimization dynamics and constraints to iteratively refine the search space from simulation feedback. We further introduce \textsc{AMS-SizingBench}, an open benchmark comprising 24 diverse AMS circuits in SKY130 CMOS technology, designed to evaluate adaptive optimization policies under realistic simulator-based constraints. \textsc{AutoSizer} experimentally achieves higher solution quality, faster convergence, and higher success rate across varying circuit difficulties, outperforming both traditional optimization methods and existing LLM-based agents.

Designing electronic circuits requires engineers to choose precise sizes for thousands of transistors so that everything works correctly. This "transistor sizing" process is slow because small changes have unpredictable effects and there are countless combinations to try. Current software tools search through options blindly, while AI language models can reason but struggle with precise numerical optimization. We built AutoSizer, which uses an AI language model as a strategist that understands the circuit and directs specialized optimization algorithms to find good transistor sizes. It learns from each round of results. if a design falls short, the AI analyzes why, adjusts its strategy, and tries again. We also created a public benchmark of 24 circuit designs for fair evaluation.