QiMeng-ChipV-RTL: Exploiting Information Locality for IP-level Verilog Generation

The generation of Register-Transfer Level (RTL) code is a crucial yet labor-intensive step in digital hardware design, traditionally requiring engineers to manually translate complex specifications into thousands of lines of synthesizable Hardware Description Language (HDL) code. While Large Language Models (LLMs) have shown promise in automating this process, existing approaches—including fine-tuned domain-specific models and advanced agent-based systems—struggle to scale to industrial IP-level design tasks. We identify three key challenges: (1) handling long, highly detailed documents, where critical interface constraints become buried in unrelated submodule descriptions; (2) generating long RTL code, where both syntactic and semantic correctness degrade sharply with increasing output length; and (3) navigating the complex debugging cycles required for functional verification through simulation and waveform analysis. To overcome these challenges, we propose \textit{ChipV-RTL}, a multi-agent framework that leverages \textit{information locality} in modular hardware design. ChipV-RTL decomposes the long-document to long-code generation problem into a set of short-document, short-code tasks, enabling scalable generation and debugging. Specifically, ChipV-RTL integrates hierarchical document partitioning, task planning, localized code generation, interface-consistent merging, and AST-guided locality-aware debugging. Experiments on \textsc{RealBench}, an IP-level Verilog generation benchmark, demonstrate that ChipV-RTL substantially outperforms state-of-the-art (SOTA) LLMs and agents, achieving a pass rate of 45.0\% compared to 21.6\%. Code, project page are available at: \url{https://iprc-dip.github.io/ChipV-RTL/}.

Designing modern chips requires engineers to translate lengthy design documents into hardware implementations, followed by extensive testing and debugging. Recent AI systems have shown promise for automating this process, but they often struggle with large industrial designs because important information is scattered across long documents, and errors can be difficult to identify and fix. Our work is based on a simple observation: in complex chip designs, most design decisions depend on only a small portion of the specification. We call this property information locality. ChipV-RTL leverages this idea by breaking a large design task into many smaller tasks, allowing AI to focus on the most relevant information at each step. The system then combines the results and automatically helps resolve errors. Experiments on IP-level design tasks show that ChipV-RTL achieves substantially higher success rates than existing LLM-based approaches. Our results suggest that exploiting information locality can make AI-assisted hardware design more reliable and scalable.