RulePlanner: All-in-One Reinforcement Learner for Unifying Design Rules in 3D Floorplanning

Floorplanning determines the coordinate and shape of each module in Integrated Circuit. With the advancement of technology node, in floorplanning stage especially 3D scenarios with multiple stacked layers, it has become increasingly challenging to adhere to complex hardware design rules. Current methods are only capable of handling specific and limited design rules, while violations of other rules require manual and meticulous adjustment. This leads to labor-intensive and time-consuming post-processing for expert engineers. In this paper, we propose an all-in-one deep reinforcement learning-based approach to tackle these challenges, and design novel representations for real-world IC design rules that have not been addressed by previous approaches. Specifically, the processing of various hardware design rules is unified into a single framework with three key components: 1) novel matrix representations to model the design rules, 2) constraints on the action space to filter out invalid actions that cause rule violations, and 3) quantitative analysis of constraint satisfaction as reward signals. Experiments on public benchmarks demonstrate the effectiveness and validity of our approach. Furthermore, transferability are well shown on unseen circuits. Our framework is extensible to accommodate new design rules, thus providing flexibility to address emerging challenges in future chip design.

Modern computer chips contain many functional modules that must be carefully arranged before the chip can be manufactured. This step, called floorplanning, is especially difficult for advanced 3D chips, where modules are stacked across multiple layers. Engineers must satisfy many design rules at the same time, such as avoiding overlap, aligning related modules across layers, and placing connected components close to each other. Existing automated methods usually handle only a small subset of these rules, so experts often need to manually fix the remaining violations. We developed RulePlanner, a reinforcement learning method that learns how to place chip modules while respecting multiple design rules together. Instead of treating each rule separately, our method represents different rules in a unified way, filters out invalid placement choices, and gives the learning system feedback based on how well the rules are satisfied. This work can reduce the amount of manual correction needed in chip design and make automated floorplanning more practical for complex 3D integrated circuits. It also provides a flexible framework that can be extended to new design rules as future chips become more advanced.