Two-Stage Unit Tying for Simplifying Differentiable Logic Gate Networks

Differentiable logic gate networks map directly to gate-level circuits, enabling ultra-low-latency inference, yet their logic footprint often exceeds FPGA capacity budgets. Tightly fitting a trained model to a target FPGA requires a post-training mechanism to trade off network complexity and accuracy—analogous to pruning in standard neural networks. To this end, we introduce unit tying: a simplification that forces selected gates to constants (0 or 1), enabling constant propagation and downstream logic elimination. However, we observe that naively extending pruning criteria to logic networks is unreliable under such near-discrete modifications. We therefore propose a two-stage algorithm for unit tying: (i) a fast Gauss–Newton screening step under a teacher-referenced logit-distortion objective that constructs a high-recall overshoot set and (ii) a refinement step that corrects approximation and interaction-driven errors using a small number of finite-difference evaluations. On CIFAR-10 and MNIST, our method consistently improves the accuracy–area trade-off over common saliency baselines, yielding substantial post-synthesis LUT reductions of up to 48% on CIFAR-10 and 43% on MNIST, with modest accuracy degradation.

Modern AI models often rely on complex arithmetic, which can be costly on hardware. An alternative is to use models whose basic operations are logic gates. Differentiable logic gate networks follow this idea by learning models that can be mapped directly to gate-level circuits, enabling very low-latency execution in hardware. However, this hardware-friendly structure does not guarantee that the resulting circuit will fit on a practical FPGA. On CPUs or GPUs, an oversized model may still run more slowly; on an FPGA, a circuit exceeding the available space may not run at all. This is difficult to avoid during training because the final circuit size is determined only after circuit optimization. We introduce a post-training method that simplifies a trained logic-gate network to fit a target FPGA. We approach logic-level compression as unit tying, where the outputs of selected units are fixed to constants such as 0 or 1. Our algorithm chooses which units to fix so that circuit optimization tools can remove unnecessary parts while changing the model’s predictions as little as possible. By reducing circuit size while preserving most of their accuracy, our method helps models that were previously too large fit on FPGA.