Poster Thu, Jul 9, 2026 • 1:00 AM – 2:45 AM PDT HALL A #4202

DITRON: Distributed Multi-level Tiling Compiler for Parallel Tensor Programs

Size Zheng ⋅ Xuegui Zheng ⋅ Hanshi Sun ⋅ Qi Hou ⋅ Wenlei Bao ⋅ Shiyu Li ⋅ Haojie Duanmu ⋅ Jin Fang ⋅ Chenli Xue ⋅ Chenhui Huang ⋅ Yuanqiang Liu ⋅ Renze Chen ⋅ Ningxin Zheng ⋅ Dongyang Wang ⋅ Li-Wen Chang ⋅ Liqiang Lu ⋅ Yun Liang ⋅ Jidong Zhai ⋅ Xin Liu

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Abstract

The scaling of large language models (LLMs) is currently bottlenecked by the rigidity of distributed programming. While high-performance libraries like CuBLAS and NCCL provide optimized primitives, they lack the flexibility required for rapidly evolving model architectures. Conversely, existing tensor compilers fail to address the complex memory hierarchy of distributed clusters effectively. To bridge this gap, we propose DITRON, a scalable tile-level compiler that democratizes high-performance distributed kernel development. DITRON introduces a novel hierarchical programming abstraction spanning Core, Device, and Task levels to map tensor programs efficiently onto heterogeneous distributed hardware. This abstraction allows DITRON to support diverse parallelism strategies while abstracting away the complexity of inter-node and intra-node communication. Evaluated across large-scale clusters, DITRON achieves performance parity with or exceeding expert-tuned CUDA libraries, delivering speedups of 6%–30% on isolated kernels and 5%–30% on end-to-end inference in vLLM. Furthermore, DITRON demonstrates strong portability, achieving significant speedups on both NVIDIA and AMD platforms.