UniRTL: Unifying Code and Graph for Robust RTL Representation Learning

Developing effective representations for register transfer level (RTL) designs is crucial for accelerating the hardware design workflow. Existing approaches, however, typically rely on a single data modality, either the RTL code or its associated graph-based representation, limiting the expressiveness and generalization ability of the learned representations. For RTL, the control data flow graph (CDFG) offers a comprehensive structural representation that preserves complete information, while the code modality explicitly encodes semantic and functional information. We argue that integrating these complementary modalities is essential for a thorough understanding of RTL designs. To this end, we propose UniRTL, a multimodal pretraining framework that learns unified RTL representations by jointly leveraging code and CDFG. UniRTL achieves fine-grained alignment between code and graph through mutual masked modeling and employs a hierarchical training strategy that incorporates a pretrained graph-aware tokenizer and staged alignment of text (i.e., functional summary) and code prior to graph integration. We evaluate UniRTL on two downstream tasks, performance prediction and code retrieval, under multiple settings. Experimental results show that UniRTL consistently outperforms prior methods, establishing it as a more robust and powerful foundation for advancing hardware design automation.

Modern chips are designed using hardware code, but understanding whether a design is efficient or finding reusable designs can still require slow and costly engineering steps. Our work studies how to build better AI representations of register transfer level (RTL) designs, which are hardware blueprints used before a chip is physically implemented. Existing methods usually look at either the source code or a graph of how data flows through the design, but each view misses useful information from the other. We propose UniRTL, a learning framework that combines both views so the model can understand what the code says and how the underlying circuit structure behaves. UniRTL learns to align specific code elements with their corresponding graph components, helping it form richer representations of hardware designs. In experiments, UniRTL improves performance prediction and code retrieval compared with prior methods, which can help hardware designers get faster feedback, reuse existing designs more effectively, and accelerate the chip design workflow.