AnalogVerifier: A Neuro-Symbolic Framework for Analog Circuit Verification

Analog circuits constitute the indispensable interface between physical reality and digital computation, underpinning safety-critical systems from autonomous driving to medical implants. Consequently, verification correctness is paramount; yet, it remains the critical bottleneck in hardware design, consuming over 50\% of engineering cycles due to a heavy reliance on the manual interpretation of unstructured, heterogeneous specifications. While Large Language Models (LLMs) offer automation potential, their probabilistic, autoregressive nature is structurally misaligned with the strict determinism required for analog verification, struggling with semantic dispersion, latent causal dependencies, and numerical precision. To bridge this gap, we introduce AnalogVerifier, a neuro-symbolic framework that automates end-to-end testbench generation by decoupling semantic translation from logical enforcement. It comprises four parts: (1) Context-Aware Task Serialization transforms complex specifications into atomic tasks via an agentic workflow; (2) Graph-Symbolic Scheduling satisfies analog design constraints through Port Dependency Graphs (PDG) for correct-by-construction sequencing; (3) Numerical-Symbolic Grounding mitigates numerical hallucination by delegating threshold derivation to a deterministic symbolic oracle; (4) Closed-Loop Repair enables correctness and completeness of the generated testbenches by simulation feedback. Evaluation on five industrial analog circuits demonstrates that AnalogVerifier achieves 82.3\%--100\% functional pass rate, establishing a new paradigm for reliable, automated analog verification.

Analog circuits connect digital computers to the physical world, powering critical systems like medical implants and self-driving cars. Ensuring their correctness is essential, yet testing them requires months of manual effort to decipher dense engineering documents and write test programs. Standard AI struggles to automate this because it often invents incorrect numbers and misunderstands physical rules. To solve this, we built Analog Verifier, a system that combines AI's reading comprehension with strict mathematical logic. First, the AI extracts key parameters from complex technical manuals. Then, instead of letting the AI guess the math, deterministic algorithms calculate exact testing thresholds and sequences. This hybrid approach prevents the system from hallucinating or breaking physical laws. Evaluated on real-world industrial circuits, our system automatically generated accurate test programs with up to a 100% success rate. This drastically reduces manual verification time, paving the way for faster and safer electronic device development.