Beyond Tokens: Enhancing RTL Quality Estimation via Structural Graph Learning

Estimating the quality of register transfer level (RTL) designs is crucial in the electronic design automation (EDA) workflow, as it enables instant feedback on key performance metrics like area and delay without the need for time-consuming logic synthesis. While recent approaches have leveraged large language models (LLMs) to derive embeddings from RTL code and achieved promising results, they overlook the structural semantics essential for accurate quality estimation. In contrast, the control data flow graph (CDFG) view exposes the design's structural characteristics more explicitly, offering richer cues for representation learning. In this work, we introduce StructRTL, a novel structure-aware graph self-supervised learning framework for improved RTL design quality estimation. By learning structure-informed representations from CDFGs, StructRTL significantly outperforms prior art on various quality estimation tasks. To further boost performance, we incorporate a knowledge distillation strategy that transfers low-level insights from post-mapping netlists into the CDFG-based predictor. Experimental results demonstrate that StructRTL establishes new state-of-the-art results, highlighting the effectiveness of combining structural learning with cross-stage supervision.

Designing chips is slow because engineers often need to run time-consuming synthesis tools to know whether a hardware design will be efficient. Our work asks whether machine learning can provide this feedback earlier, directly from register transfer level (RTL) code, before full synthesis. We introduce StructRTL, a model that represents RTL designs as control data flow graphs (CDFGs), which capture how data and control signals move through a circuit. Instead of reading hardware code only as text, StructRTL learns from the structure of the design using graph-based self-supervised learning. It also uses knowledge from synthesized circuits during training to improve its predictions, while remaining fast at inference time. Our experiments show that StructRTL predicts post-synthesis area and delay more accurately than prior graph-based and language-model-based methods. It also generalizes to industrial RTL designs and provides much faster feedback than synthesis. This can help hardware engineers compare design alternatives quickly, reduce costly trial-and-error, and accelerate early-stage chip design.