EDA Bench: Functional Failure Modes in PCB-Generating Agents

Language-model agents are increasingly able to operate electronic design automation tools: they can search datasheets, select components, edit KiCad projects, run design checks, and iterate after failures. These capabilities create a new class of artifact-level failure modes. An agent can produce a syntactically valid or visually plausible printed-circuit-board project while failing to realize the external electrical behavior required by the target design. We introduce \edabench{}, an execution-based benchmark for exposing functional failure modes in language-model agents that perform KiCad PCB reconstruction. \edabench{} contains 35 released tasks derived from public open-hardware projects spanning connector breakouts, power-path circuits, microcontroller systems, motor drivers, camera and compute adapters, and high-density carriers. Each harness receives a prompt and a standard KiCad environment, then must produce a complete KiCad project. Submissions are graded by an oracle that parses the realized PCB, extracts routed copper, checks declared external ports, models trace parasitics and short faults, runs ngspice simulations, and applies KiCad ERC and DRC checks. The score is based on observable external-I/O behavior rather than text overlap, screenshot similarity, component inventory, or reference-designator matching. We validate the artifact with reference, fail, and mutation canaries: all 35 released frozen references score 1.0, and all 35 released structural-failure canaries score at most 0.15. Initial baselines show that the strongest evaluated web-enabled harness scores 4.58\% overall, building 21 of 35 projects while failing most functional checks. These results isolate a recurring failure mode for engineering agents: parseable or plausible PCB artifacts are not necessarily electrically functional artifacts.