Chip Placement with Diffusion Models

Macro placement is a vital step in digital circuit design that defines the physical location of large collections of components, known as macros, on a 2D chip. Because key performance metrics of the chip are determined by the placement, optimizing it is crucial. Existing learning-based methods typically fall short because of their reliance on reinforcement learning (RL), which is slow and struggles to generalize, requiring online training on each new circuit. Instead, we train a diffusion model capable of placing new circuits zero-shot, using guided sampling in lieu of RL to optimize placement quality. To enable such models to train at scale, we designed a capable yet efficient architecture for the denoising model, and propose a novel algorithm to generate large synthetic datasets for pre-training. To allow zero-shot transfer to real circuits, we empirically study the design decisions of our dataset generation algorithm, and identify several key factors enabling generalization. When trained on our synthetic data, our models generate high-quality placements on unseen, realistic circuits, achieving competitive performance on placement benchmarks compared to state-of-the-art methods.

When designing chips, the positioning (or placement) of circuit components plays a pivotal role in determining the performance and power consumption of the resulting chip. We trained a generative model, similar to those used for image generation, to create near-optimal placements for any given circuit. However, very few training examples are publicly available, since many chip designs are closely-guarded secrets. To overcome this, we devised a method to generate large amounts of synthetic data from scratch, allowing us to train large models without the use of any real chip designs. Our models produce better placements using less time than existing techniques, potentially helping designers produce cheaper, faster chips.